Biography, Gary Giust Ph.D.

Dr. Giust has been teaching jitter to industry professionals since 2003. A background in analog design for various high-speed communications products and advanced process technology development provides a foundation for Dr. Giust to analyze jitter from various points of view. For years he has provided customer technical support as an applications engineer for high-performance timing solutions spanning a broad range of end markets, including high-speed physical layer devices and applications. This work offers exposure to a wide variety of problems engineers encounter while working with jitter, and ways to resolve them.

Dr. Giust has co-authored a book on timing issues, is a guest columnist for EDN magazine, is a past Technical Chair for Ethernet Alliance's Backplane Subcommittee (IEEE 802.3ap), has published internationally in various trade and refereed journals, holds 15 patents, and has volunteered as Chair and Vice-Chair for IEEE PACE. His popular jitter courses are available to industry professionals publicly through the University of California Santa Cruz extension, and privately at various corporations.

Systems Experience

• Dr. Giust worked previously as a principal application engineer at AMCC focused on high-speed datacom/telecom applications. Before that he was a product-line manager for frequency control products at PhaseLink Corp., supporting applications demanding the lowest jitter and phase noise in the industry. He previously worked as a prinicipal application engineer within Cypress Semiconductor's Timing Technology Division, supporting a diverse portfolio of 70+ timing products including jitter attenuators, PLL and non-PLL buffers, clock generators, skew-control devices, MUXes, and cross-point switches.
• This experience exposed, and continues to expose, Dr. Giust to a multitude of customers' system-related jitter issues and ways to resolve them. He has spent much time in the lab measuring and troubleshooting a wide variety of customer issues related to jitter and phase noise. Much of this work has been in support of high-speed industry standards (such as PCI, PCIX, PCIe, SONET/SDH, Ethernet, Fibre Channel, SMPTE 259/292, OBSAI, CPRI, DOCSIS, SATA, etc.).

High Speed Design

• As an analog designer for Cypress' Datacom Division (2001-2003), Dr. Giust designed various high-speed blocks for SERDES (0.2-10.7 Gbps) ICs supporting standards including Ethernet, Fibre Channel, SONET/SDH, and SMPTE. Typical designs included PLLs, amplifiers, and other blocks using deep submicron CMOS, and SiGe BiCMOS processes.
• This experience provided an intimate knowledge of PLL design and loop dynamics, high-speed design and signal integrity, and related jitter issues. Vital aspects of this work included simulating jitter, board-level debugging, troubleshooting, and characterizating jitter to guarantee compliance to various serial standards.